1. Field of the Invention
The present invention relates to non-volatile memory devices and, more particularly, to non-volatile memory devices having two bits per cell.
2. Description of Related Art
A non-volatile semiconductor memory device is designed to maintain programmed information even in the absence of provided power. The read-only memory (ROM) is a non-volatile memory device commonly used in electronic equipment such as microprocessor-based digital electronic equipment and portable electronic devices such as cellular phones.
ROM devices are conventionally arranged into a plurality of memory cell arrays. Each memory cell includes a transistor, which typically comprises a metal-oxide-semiconductor field effect transistor (MOSFETs) that is juxtaposed between two intersecting bit lines and a word line. Data bit values or codes held by these memory cell transistors are permanently stored (until deliberate erasure) in the physical or electrical properties of the individual memory cells. Generally speaking, a consequence of the non-volatile nature of a ROM is that data stored in the memory device can only be read.
A relatively recent development in non volatile memory has been the advent of Nitride-Read Only Memory (NROM) devices. NROM devices offer a number of advantages over the 30 year old currently dominant floating gate devices such as EPROM, Flash, and EEPROM, which store charge in a conductive floating gate.
NROM cells can comprise 2 bit flash cells based on charge storage in an Oxide-Nitride-Oxide (ONO) dielectric. The NROM cell may comprise an n-channel MOSFET device wherein nitride is used as a trapping material between a top and bottom oxide. The ONO structure replaces the gate dielectric that is used in floating gate devices. The top and bottom oxide layers should be thicker than 50 A to prevent any oxide damaging direct electron tunneling during programming.
NROM flash blocks may be added to standard CMOS processes by laying down the ONO layer after the field isolation but before the gate oxidation. Adding the NROM components typically has minimal effects on the CMOS thermal budgets. The NROM memory cells can be programmed by channel hot electron (CHE) injection, and erased by tunneling enhanced hot hole (TEHH) injection through the bottom oxide. The NROM cells operate as localized charge storage devices, which allows the trapped charge to remain only at the injection point. Thus, single bit failures commonly experienced by floating gate technologies may be reduced. This reduction may allow for further minimization of device size and increased device density without degradation in performance.
NROM devices can offer a number of significant advantages over floating gate devices. Both the bit-size and the die size can be a factor of 3 or more smaller for NROM devices. NROM devices can also require 6 to 8 fewer photomask steps, their process complexity can be simpler, and it can be easier to integrate them with CMOS devices for embedded applications. Furthermore, NROM devices can be more suited to low voltage product implementation due to a lower erased threshold voltage. However, a common problem with NROM devices can be the lateral leakage of trapped charge over the ONO layer edge. Another problem that may occur with manufacturing memory devices having critical dimensions (CD) below around 0.15 μm, is a failure to properly resolve the device geometries when undergoing photolithographic processing.